Mentor Graphics Announces FPGA Advantage 5.2

WILSONVILLE, Ore.--(BUSINESS WIRE)--Oct. 31, 2001--Mentor Graphics Corporation (Nasdaq:MENT - news) today introduced FPGA Advantage® 5.2, a new version of its industry-leading HDL design flow that provides designers with an integrated environment for design creation, management, simulation and synthesis of FPGAs.

FPGA Advantage 5.2 delivers new documentation features that improve design creation and design reuse, and synthesis enhancements that generate more accurate timing data. Enhancements across the entire flow provide designers with a smoother and more robust design solution that simplifies the creation of complex FPGAs and programmable logic devices.

"FPGA Advantage 5.2 includes our most robust feature-set to date, including best-in-class features for design documentation and creation, and incremental synthesis for complex designs," said Valerie Rachko, director of marketing for FPGA Advantage. "With this release, we achieved smoother integration between stages in the flow, enabling designers to move seamlessly between design creation, synthesis and simulation at the push of a button."

New Documentation Features Encourage Design Reuse

A common bottleneck in design reuse has been the time expended importing legacy code into a new design. FPGA Advantage 5.2 includes a new recursive file search feature that allows designers to quickly set up and search through a directory of IP files to import a complex design. Designers can view the reused design's structure prior to design inclusion, enabling smoother integration of legacy code.

FPGA Advantage 5.2 also includes new HTML documentation that allows companies to share designs across a secure Web site. The designs are presented in an easy-to-understand format that shows both design hierarchy and the relationships between different hardware descriptions.

Improvements have also been made to the HDL2Graphics(TM) conversion engine in FPGA Advantage 5.2. The new version includes support for incremental code recovery. When incremental changes are made in text, FPGA Advantage 5.2 makes it easy to identify where the change was made in the corresponding graphical view.

Mentor Improves Patented Interface-Based Design Technology

Mentor's newly patented Interface-Based Design(TM) (IBD) technology allows designers to simplify interconnect creation problems by displaying design interconnect structures in an easy-to-view and compact tabular format. FPGA Advantage 5.2 includes new global signal and comment columns that improve the readability of generated HDL code, enabling designers to easily tag selected elements of a design. Improvements to IBD have also streamlined the downstream synthesis flow. Designers can now set synthesis attributes on any net, port, block and component and have these attributes transferred automatically to the synthesis engine.

FPGA Advantage 5.2 Improves Timing Results

FPGA Advantage 5.2 now extends support of the Mentor Graphics® TimeCloser(TM) synthesis technology to Altera, with Altera's Quartus®-II design environment. The TimeCloser technology enables designers to optimize true critical paths based on the physical data generated by the place and route tool. With advanced optimization techniques to generate the synthesis timing results to drive place and route, the overall device performance is improved, helping designers achieve better timing results with minimum iterations.

Pricing and Availability

FPGA Advantage 5.2 is available immediately through Mentor Graphics' unique multi-tiered distribution network. All versions of FPGA Advantage 5.2 support all major FPGA vendors. Customers have the ability to choose from an entry-level FPGA design flow solution designed for the single FPGA designer, starting at $12,000, to a complex FPGA design flow solution for workgroups starting at $45,000. Additional information on FPGA Advantage 5.2 can be found on the World Wide Web at www.fpga-advantage.com.

About Mentor Graphics Corporation

Mentor Graphics Corporation (Nasdaq:MENT - news) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $600 million and employs approximately 3,000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Ore. 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, Calif. 95131-2314. World Wide Web site: www.mentor.com.

Mentor Graphics and FPGA Advantage are registered trademarks of Mentor Graphics Corporation. Interfaced-Based Design and TimeCloser and trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

     Mentor Graphics
     Rebecca Granquist, 503/685-0702
     rebecca_granquist@mentor.com
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     Jason Khoury, 415/352-2628
     jason_khoury@benjamingroup.com